The present application relates to semiconductor technology. More particularly, the present application relates to a semiconductor structure including a multi-faceted epitaxial semiconductor structure within both a source region and a drain region and on exposed surfaces of a semiconductor fin. The present application also relates to a method of forming the semiconductor structure of the present application.
The use of non-planar semiconductor devices such as, for example, fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Fin field effect transistors (FinFETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
In typically FinFET devices, an epitaxial semiconductor material structure having a faceted surface is grown from the exposed surfaces of each semiconductor fin and merging of the individual epitaxial semiconductor material structures generally occurs. In such instances, the contact structures can only be formed on the exposed topmost horizontal surface of the merged epitaxial semiconductor material structures. As such, the contact resistance and spreading resistance of conventional FinFET devices is very high. A method is thus needed that can reduce the contact resistance and spreading resistance of FinFET devices.